Xelic Founders
Mark
Gibson
President
Mark brings to Xelic sixteen years of project management and design experience. His leadership and organizational skills have played a key role in the success of many projects and companies. Mark's ability to quickly understand the customer's needs, develop advanced architectures and execute time critical projects swiftly and efficiently has been the cornerstone to his success. Before founding Xelic, Mark was a Technical Manager and Principal Engineer at Mint Technology. Mark managed and participated in numerous multi-million gate ASIC develop teams all of which had first pass silicon success. Mark was instrumental in winning and leading Mint Technology's first full outsource ASIC project, a SONET OC-192 forward error correction chip. He is also a leader in high speed clocking, system design, architecture definition and verification. Mark also ran his own consulting company and was a senior engineer at ABB, a multi-national process control company. His areas of expertise run the gamut from 10/100/1000 Ethernet and proprietary network solutions to large distributed fault tolerant process control systems. Mark holds a Bachelor of Science in Electrical Engineering from Rochester Institute of Technology.
Doug
Bush
IP Development
Doug has over 15 years of development experience in the areas of SONET/SDH, Digital Wrapper, ASIC, and firmware engineering. Prior to founding Xelic, Doug held a leadership position at Mint Technology as a Principal ASIC Engineer. His extensive communications and SONET/SDH knowledge contributed significantly to the awarding of two major SONET/SDH OC-192 ASIC contracts for Mint Technology. Doug has held several leadership roles for both architecture and design. In addition to his RTL and verification skills, Doug has developed several reference designs showcasing the features of various SONET/SDH chipsets operating at data rates from 155Mb/s to 622Mb/s. His ability to assist and advise others has proven to be a valuable asset when interfacing with customers. Doug has published several high-speed communications white papers and is dedicated to success and the highest standards of quality. Doug holds a Bachelor of Science in Electrical Engineering with honors from Rochester Institute of Technology and a Master of Science in Electrical Engineering from the University of Maine.
Mark
Grabosky
Design Methodology
Mark leads the methodology effort in the areas of ASIC architecture, design, and synthesis at Xelic. Mark brings to Xelic over fifteen years of experience in system architecture, ASIC design, and firmware development. Prior to founding Xelic, Mark was a Principal ASIC Engineer at Mint Technology where he played a key roll in the architecture and design of high speed multimillion gate ASIC's. Mark has taken the lead in the development of systems involving technologies ranging from digital imaging to satellite communications to high-speed SONET/SDH. His experience in developing and refining architectures, RTL design, synthesis, and timing closure along with his attention to detail has consistently led to first pass success. Adding to this, Marks' background in embedded system design, applications engineering, and semiconductor device physics gives him the ability to quickly identify solutions throughout the entire development cycle. Mark has also held leadership positions at National Semiconductor and Eastman Kodak. Mark holds a Bachelor of Science in Micro Electronics Engineering from the Rochester Institute of Technology and has completed his Masters work in Electrical Engineering at the Rochester Institute of Technology.
Dave
Wurthmann
Verification Methodology
This long time ASIC veteran started his career in 1986 in a small ASIC group at Digital Equipment Corporation. Dave's expertise lies in ensuring timely first-pass silicon. Having been responsible for everything from hand placement of small ASIC designs to architecture and implementation of sophisticated client/server based ASIC verification systems; he is intimately familiar with all aspects of the ASIC design flow. Dave has worked in high profile positions in consulting firms, for semiconductor vendors and in system houses from Boston to Silicon Valley always within the ASIC domain. Over the past three years, as a Principal ASIC Engineer at Mint Technology, Dave has been a key contributor on high-speed SONET/SDH communications chips, helping to bring aggressively paced startups to market with ground breaking technologies. His leadership experience in project management, design, marketing, and even cost accounting make him an indispensable asset to the company. Dave has also held leadership roles at Actel and Toshiba. Dave holds a Bachelor of Science (Cum Laude) in Electrical Engineering from Rochester Institute of Technology.