XCPOS
POS Processing up to 10 Gbit/s
| Document | Size | View PDF | Download | Register |
|---|---|---|---|---|
| Product Brief | On Road Map |  Register
for access to restricted documents. |
||
| Datasheet | On Road Map | |||
| Fact Sheet | On Road Map | |||
General Description
The Xelic POS Processor is a full duplex standards based core designed for integration with customer proprietary intellectual property.
The transmit POS processor is responsible for reading packets from the transmit FIFO and creating the outgoing HDLC-like frames to be mapped into the SONET/SDH SPE. The POS processor performs rate adaptation by inserting flag characters (0×7E) when no packets are available for transmission.
One of two polynomial generators can be used to generate the FCS, either CRC-16 or CRC-32.
Prior to scrambling the POS frame the byte stuffing block control escapes all flag (0X7E) and control escape (0×7D) characters for transparency.
The receiver delineates the input data stream removing flags and idle frames. FCS validation is performed using either CRC-16 or CRC-32 (programmable).
The XCPOS includes performance monitors for TX_Packet_Count, TX_Abort_Frame_Count, RX_Frame_Count, RX_FCS_Error_Count, RX_Abort_Frame_Count, RX_Min_Len_Count, and RX_Max_Len_Count.
Features
- Designed for ASIC and/or FPGA implementations
- Complies with RFC 1662 PPP and RFC 2615 PPP standards
- Inserts and checks CRC-16 or CRC-32 FCS
- Performs byte stuffing/de-stuffing
- Configurable bus width
- Performance monitor
Please contact cores@xelic.com for additional information.