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XCS48F
STS48/STM16 Framing/Transport Processing

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Product Brief 83.6 KB View PDF Download PDF Register for access to restricted documents.
Datasheet 545 KB View PDF Download PDF
Fact Sheet 226 KB View PDF Download PDF

General Description

The Xelic SONET/SDH STS-48/STM-16 Framer is a flexible standards based core ideally suited for integration with customer proprietary intellectual property for a variety of networking applications.

Full duplex operation combines transmit and receive functions with configurations for bypass, streaming, and mapping modes of operation at a data rate of 2.5Gb/s.

The XCS48 transmitter performs B1/B2/B3 parity calculation and insertion, scrambling, and the insertion of transport and path overhead from an external overhead port or through internal register programming.

The XCS48 receiver byte aligns incoming data, de-scrambles appropriate frame byte locations, performs pointer processing for contiguous concatenated payloads, detects error conditions, accumulates various condition counts, and extracts transport and path overhead information to both internal register locations and external overhead ports.

A standard processor interface is provided for internal register configuration and the reporting of status, interrupt, and performance monitoring information.

Various test modes are available for diagnostic purposes to transport fixed value payload information, force selected error conditions, and corrupt data to verify various interpreter algorithms and error counter operations.

Features

  • Designed for ASIC and/or FPGA implementations
  • Complies with GR-253-CORE, ITU-T G.707, G.783, and ANSI T1.105 standards
  • Flexible core architecture includes variable size data bus widths of 8 to 128 bits
  • Supports transmit and receive facility and terminal loopback configurations
  • Accepts streaming SONET/SDH frames or mapped client signals for transport
  • Flexible insertion and extraction of transport and path overhead byte information
  • Programmable general purpose registers available for the insertion and extraction of any frame transport or path overhead location
  • Data corruption available through internal register programming for debug or test purposes
  • Performs SONET/SDH frame alignment with LOS and LOA detection
  • Programmable detection of LOF and OOF error conditions
  • Generates line AIS SONET/SDH frames for LOS and/or LOF error conditions
  • Supports scrambling/descrambling (1+x6+x7) with polynomial corruption capability for diagnostics
  • Programmable counters for user defined interval or errored second accumulation
  • Detects and accumulates B1/B2/B3 parity, path REI, and line REI error conditions in configurable bit or block error counters
  • Detects APS conditions (including line AIS and line RDI) and implements programmable acceptance count criteria
  • Provides insertion and extraction of section trace (J0) messages for 16 or 64 byte lengths and optional legacy J0/Z0 support
  • Provides insertion and extraction of path trace (J1) messaging
  • Detects path RDI and path REI error conditions
  • Detects LOP, Path AIS, and concatenation error conditions
  • Internal counters to track pointer increments and decrements
  • Generates frame start, SPE valid, SPE start, and transport/path overhead port control signals

Please contact cores@xelic.com for additional information.

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